About the role

<div class="content-intro">Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here.  </div>As the Senior FPGA Engineer at Ambiq, you will drive the development and rendering of FPGA images in support of our pre-silicon prototyping environments.     In this role, you will work with our SoC design, software development, design verification, and system test teams as our primary internal customers for the FPGA images.     The successful candidate will have experience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase.   The person in this role must be comfortable working with RTL to implement specialized changes to the SoC database for the FPGA development flow. This role will require defining and implementing internal and external FPGA timing constraints to enable repeated delivery of design iterations to the software and validation teams. The candidate will be required to debug RTL designs using FPGA tools, external logic analyzers, and protocol analyzers.  Responsibilities  <ul> <li data-leveltext="" data-font="Symbol" data-listid="40" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="40" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Implement and debug FPGA designs on a Stratix-10 development board using Intel Quartus prime Pro.  </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="40" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Support a regression test-suite consisting of system-level test cases to validate updated FPGA builds.  </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="40" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Assist development teams in reproduction, triage, and debug of issues both pre-silicon and post-silicon </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="40" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Define and implement timing constraints. </li> </ul> Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">BSEE or BSCE with 6+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Solid experience with defining timing constraints for Static Timing Analysis. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Some familiarity with Cadence SoC design flow. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Solid understanding of the tool flow from RTL to bitstream. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Some familiarity with programming in C language. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Familiarity with source code control systems (git) required. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Familiarity with simulation tools. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="41" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Hands-on lab bring-up experience, debug, and instrument usage. </li> </ul> In addition, the following areas of experience are highly desirable for the position but not strictly required:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">In-depth experience with Stratix 10 FPGA platforms: boards, debug, performance, and throughput tuning. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">In-depth experience with AMD VU19P prototyping systems, debug, design partitioning, performance, and throughput tuning. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Experience with Siemens proFPGA prototyping/emulation platform and VPS software. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Experience with ARM’s MPS4 platform. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Experience with low power designs. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Experience with embedded microprocessors. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Proven design validation skills. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">In-depth experience writing Verilog code. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Experience with System Verilog verification environments. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Good analytical skills. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Python script experience. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1">YAML </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="42" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1">Peripheral protocols: I2C, I3C, MSPI, UART, USB </li> </ul>

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ambiqmicroinc

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