Staff/ Principal Architect

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <div> <p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at&nbsp;<a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p> </div> <div> <p><strong>Role Overview</strong></p> <p>We are seeking an experienced <strong>Staff/ Principal&nbsp;Architect</strong> to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.<br>This role will define next-generation architectures for AI infrastructure, working at the intersection of <strong>silicon, system, and protocol design</strong>. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.</p> <p>This is a unique opportunity to join a <strong>new and growing Israel site</strong>, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.</p> <p data-path-to-node="4"><strong><span data-contrast="none">Key Responsibilities</span></strong>&nbsp;</p> <ul> <li>Define and drive <strong>system and chip-level architecture</strong> for high-speed connectivity products</li> <li>Lead architecture for <strong>PCIe-based interconnects</strong>, networking protocols, and Ethernet subsystems</li> <li>Analyze system requirements and translate them into scalable and efficient hardware architectures</li> <li>Drive tradeoff analysis across performance, power, latency, area, and cost</li> <li>Collaborate with cross-functional teams including <strong>RTL, Physical Design, Firmware, Validation, and Product Engineering</strong></li> <li>Define and review <strong>micro-architecture specifications</strong> and ensure alignment across teams</li> <li>Contribute to <strong>standard-based and custom protocols</strong> for next-generation AI infrastructure</li> <li>Support performance modeling, simulation, and architectural validation</li> <li>Work closely with customers and partners to understand emerging use cases and requirements</li> <li>Mentor engineers and help build strong technical leadership within the Israel R&amp;D center</li> </ul> <p>&nbsp;</p> <p><strong><span data-contrast="none"><br></span>Basic Qualifications</strong></p> <ul> <li><strong>10+ years of experience</strong> in semiconductor architecture, ASIC design, or system engineering</li> <li>Strong expertise in <strong>PCIe architecture (Gen4/5/6+)</strong> and its ecosystem</li> <li>Deep understanding of <strong>Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond)</strong></li> <li>Experience designing <strong>high-speed, low-latency data paths</strong></li> <li>Solid understanding of <strong>SoC architecture and integration challenges</strong></li> <li>Experience working across full chip development lifecycle</li> <li>Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs</li> <li>Ability to influence and collaborate across multiple engineering domains</li> </ul> <p>&nbsp;</p> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <p>&nbsp;</p> <ul> <li>Experience with <strong>CXL, NVLink, UALink, or other advanced interconnect protocols</strong></li> <li>Background in <strong>AI/ML infrastructure, data center systems, or hyperscaler environments</strong></li> <li>Experience with <strong>SerDes-based systems and high-speed PHY integration</strong></li> <li>Familiarity with <strong>networking stacks, switching, or RDMA technologies</strong></li> <li>Experience with <strong>performance modeling tools and architectural simulators</strong></li> <li>Knowledge of <strong>power/performance optimization techniques at system level</strong></li> <li>Track record of driving architecture from concept to silicon</li> </ul> <p>&nbsp;</p> </div> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>