CPU Design Architect / Principal Digital Design Engineer

<p><strong>Job Description:</strong><br>Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:&nbsp;<br>- Perform CPU development and design integration for MIPS CPU subsystem. &nbsp;<br>- Explore latest technologies and be responsible for conducting fundamental research on new directions in CPU architecture &nbsp;<br>- Contribute ideas for advanced CPU performance features - analyze workloads in details, identify performance bottlenecks and opportunities, bring a data driven approach to tradeoffs in CPU design, derive architecture and micro-architecture to design/model implantation team, and bring ideas to successful silicon</p> <p><strong>Minimum Qualifications:&nbsp;</strong><br>- Master Degree in Electrical Engineering, Computer Science or Computer Engineering.&nbsp;<br>- At least 5 years of CPU related Architect/RTL/Verification/Implementation design experience &nbsp;<br>- Knowledge and practical experience with common RISC CPU architecture.&nbsp;<br>- Familiarity with chip digital design flow, including RTL integration, simulation, STA.&nbsp;<br>- Understanding of high performance techniques and trade-offs in a CPU microarchitecture &nbsp;<br>- Ability to problem solve and prove own ideas&nbsp;</p> <p><strong>Preferred Qualifications:</strong>&nbsp;<br>- PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS&nbsp;<br>- 8+ years of CPU related Architect/RTL/Verification/Implementation design experience &nbsp;<br>- Strong CPU architecture knowledge and micro-architecture knowledge &nbsp;<br>- Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture.&nbsp;<br>- Familiarity with synthesis, power analysis and post silicon debugging&nbsp;<br>- Cross-site working experience is a PLUS.&nbsp;<br>- Common knowledge in modeling/DV/OS is a PLUS.&nbsp;<br>- Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.</p> <p>#LI-DNI</p>