Design Verification and Emulation Manager

<div class="content-intro"><p>Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution</p></div><p>Efficient is looking for a seasoned <strong>Design Verification &amp; Emulation Manager</strong> to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.</p> <p>This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.&nbsp; Join our team and help us shape the future of computing at the edge and beyond!&nbsp;</p> <p><strong>Key Responsibilities&nbsp;</strong></p> <ul> <li><strong>Define end-to-end verification strategy</strong> from block-level through full-chip simulation to emulation and prototyping</li> <li><strong>Own UVM-based methodology</strong>, including constrained-random, coverage-driven closure, assertions, and formal verification adoption</li> <li><strong>Drive emulation platform strategy</strong> — platform selection, capacity planning, compilation flows, and multi-project scheduling</li> <li><strong>Enable system-level validation on emulation</strong> — processor boot, OS bring-up, firmware execution, and IO exercising</li> <li><strong>Deliver pre-silicon platforms for early software development</strong> in partnership with firmware and software teams</li> <li><strong>Establish hybrid simulation-emulation methodologies</strong> using transactor-based interfaces to maximize both environments</li> <li><strong>Own functional coverage models and sign-off criteria</strong>, driving closure across simulation and emulation combined</li> <li><strong>Lead debug and root cause analysis</strong> across simulation and emulation, driving cross-functional bug resolution</li> <li><strong>Manage verification dashboards, bug tracking, and regression health</strong> to provide clear visibility to program leadership</li> <li><strong>Build, mentor, and scale</strong> a high-performing team of verification and emulation engineers</li> <li><strong>Drive verification schedules and risk mitigation</strong> aligned with chip program milestones and tapeout readiness</li> <li><strong>Represent verification and emulation in tapeout readiness reviews</strong> and program-level decision forums</li> <li><strong>Collaborate cross-functionally</strong> with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams</li> <li><strong>Manage emulation lab infrastructure</strong>, including hardware resources, licensing, and vendor relationships</li> <li><strong>Evaluate and adopt new EDA tools and methodologies</strong>, including AI/ML-assisted verification techniques.</li> <li><strong>Define right DV&nbsp; mix for in-house&nbsp; vs outsourcing to 3rd party vendors</strong>. Coordinate 3rd party vendor resources towards achieving project goals.</li> </ul> <p><strong>Required Qualifications &amp; Experience&nbsp;</strong></p> <ul> <li><strong>Education:</strong> Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.</li> <li><strong>Experience:</strong> 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.</li> <li><strong>Verification Methodology:</strong> Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.</li> <li><strong>Emulation Platforms:</strong> Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.</li> <li><strong>Languages &amp; Tools:</strong> Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.</li> <li><strong>SoC Architecture:</strong> Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.</li> <li><strong>Leadership:</strong> Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.</li> <li><strong>Execution:</strong> Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).</li> </ul> <p><strong>Preferred Qualification</strong></p> <ul> <li>Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.</li> <li>Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.</li> <li>Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).</li> </ul> <p>We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.</p><div class="content-conclusion"><p><strong>Why Join Efficient?</strong></p> <p>Efficient offers a<span class="Apple-converted-space">&nbsp;</span><strong>competitive compensation and benefits package</strong>, including<span class="Apple-converted-space">&nbsp;</span><strong>401K match, company-paid benefits, equity program, paid parental leave, and flexibility</strong>. We are committed to personal and professional development and strive to grow together as people and as a company.</p></div>