Sr. Design Verification Engineer

<p></p> <p><strong>Location:</strong></p> <p>Hybrid, working onsite at our Bangalore offices 3 days per week.</p> <p>Minimum:</p> <ul> <li> <p>BS in Electrical Engineering, Computer Science, or a related field with 8+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 7 years of industry experience is preferred.</p> </li> <li> <p>Experience in IP/SoC verification cycle preferably from concept to tape-out to bring-up.</p> </li> <li> <p>Good knowledge of verification methodologies such as UVM/OVM, etc.</p> </li> <li> <p>Hands-on ASIC-SoC design verification tests and debug experience.</p> </li> <li> <p>Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.</p> </li> <li> <p>Good problem-solving skills and the passion to take on challenges (particularly in AI domain).</p> </li> <li> <p>Passionate about AI and thriving in a fast-paced and dynamic startup culture.</p> </li> </ul> <p>Preferred:</p> <ul> <li> <p>Part of Successful implementation of multiple verification environments and tape-out efforts.</p> </li> <li> <p>Experience with C/C++ is good</p> </li> </ul> <p>&nbsp;</p> <p>&nbsp;</p>