Senior Digital Design Engineer, IP and Methodology

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>Join Astera Labs as a&nbsp;<strong>Senior Digital Design Engineer</strong> to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up.</p> <p>You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li class="text-start "> <p><strong>RTL Design &amp; Implementation</strong></p> <ul> <li class="text-start ">Own the RTL implementation of complex digital designs from micro-architecture through sign-off</li> <li class="text-start ">Design and implement CPU subsystems and embedded processor interfaces</li> <li class="text-start ">Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments</li> </ul> </li> <li class="text-start "> <p><strong>Verification &amp; Quality</strong></p> <ul> <li class="text-start ">Collaborate with verification teams to review test plans and debug issues</li> <li class="text-start ">Support efforts to achieve timing closure and implement Design-for-Test (DFT) features</li> <li class="text-start ">Accountable for quality and overall design success with the support of senior engineers</li> </ul> </li> <li class="text-start "> <p><strong>Methodology &amp; Automation</strong></p> <ul> <li class="text-start ">Scripting and automation for ASIC methodology improvement</li> <li class="text-start ">Contribute to design infrastructure that improves team productivity and design quality</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li class="text-start ">Bachelor's degree in Electrical Engineering or equivalent</li> <li class="text-start ">3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets</li> <li class="text-start ">Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence</li> <li class="text-start ">Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)</li> <li class="text-start ">Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)</li> <li class="text-start ">Experience with clocking, CDC, and RDC methodologies</li> <li class="text-start ">Proficiency in SystemVerilog and Python in a production environment</li> </ul> <p><strong>Preferred Qualifications</strong></p> <ul> <li class="text-start ">Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)</li> <li class="text-start ">Familiarity with high-speed protocols—PCIe Gen 6/7, Ethernet, UALink, or UCI</li> <li class="text-start ">Experience with CMOS nodes (≤7nm)</li> <li class="text-start ">Exposure to embedded firmware development or secure firmware boot flows</li> <li class="text-start ">Experience with functional and formal verification at block and chip level</li> <li class="text-start ">Familiarity with UVM-based verification methodologies</li> </ul> <p>Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>