Director, Silicon Logical Design

Bristol2d ago

Seniority: Lead

About the role

About Graphcore  At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary  We are seeking a Director of Silicon Logical Design to lead and scale our Logical Design group within the Silicon department. This role is accountable for the overall strategy, technical direction, execution quality and team development for Graphcores microarchitecture and RTL design efforts.  The Director will be responsible for ensuring that our logical design methodologies, architectures and RTL implementations meet world class standards for performance, power, area, and schedule. This leader will partner closely with Architecture, Physical Design, Verification, DFT and Program Management teams to ensure successful, predictable silicon delivery aligned with Graphcores long term product roadmap.  The Team  The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director, you will guide this multi site team, strengthen cross functional collaboration, and drive the evolution of our design flows and capabilities.  Responsibilities and Duties  Leadership & Strategy  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="1">Define and execute the strategic roadmap for Logical Design, ensuring alignment with Graphcores silicon and product strategy. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Lead, grow and mentor a high performing RTL/micro architecture design organisation. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Establish and implement best in class design methodologies, documentation standards and quality metrics. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Drive continuous improvement across team structure, workflows, tooling, and design processes. </li> </ul>   Technical Ownership  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Provide technical oversight of micro architecture specification and RTL development across all major blocks and subsystems. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Guide architectural feasibility studies, contribute to architectural trade offs and micro architecture definition. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Oversee the integration of third party IP, complex application specific blocks, and high performance custom designs. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Ensure robust design sign off through high quality linting, synthesis, CDC/RDC, timing closure and coverage metrics. </li> </ul>   Cross-Functional Collaboration  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Partner closely with Physical Design, Verification, DFT, Architecture and Program Management teams to ensure cohesive planning and execution. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Foster strong communication across teams and global sites, ensuring alignment on priorities, risks and deliverables. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture. </li> </ul>   Execution & Delivery  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Own delivery of high quality, on schedule RTL for multiple parallel silicon programs. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1">Establish scalable project planning and tracking practices, including resource planning and risk mitigation. </li> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1">Champion design automation and infrastructure improvements to accelerate productivity and improve design quality. </li> </ul> Essential Skills & Experience  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Degree in Computer Science, Electrical Engineering or a related field; advanced degree preferred. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="15" data-aria-level="1">Extensive experience in digital logical design, micro-architecture and RTL development for large scale, high performance silicon projects. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="16" data-aria-level="1">Proven success leading and developing technical teams in a semiconductor environment. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="17" data-aria-level="1">Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="18" data-aria-level="1">Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.). </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="19" data-aria-level="1">Demonstrated excellence in cross functional leadership and communication across global teams. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="20" data-aria-level="1">Strong organisational skills with ability to manage multiple priorities and drive execution in fast-paced environments. </li> </ul>   Desirable Experience  <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="21" data-aria-level="1">Processor or accelerator micro architecture. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="22" data-aria-level="1">High-speed serial interfaces and complex, high bandwidth IP blocks. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="23" data-aria-level="1">Arithmetic pipeline design and floating point datapaths. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="24" data-aria-level="1">Advanced synthesis, timing analysis, power analysis, and logical equivalence checking. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="25" data-aria-level="1">Design-for-test methodologies. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="26" data-aria-level="1">Power integrity and silicon device level understanding. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="27" data-aria-level="1">Experience with silicon bring-up and post-silicon validation. </li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="28" data-aria-level="1">Program planning and multi-project execution leadership. </li> </ul>

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