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Senior Electrical Engineer, FPGA Development
True Anomaly
Long Beach1mo ago
- Seniority
- Senior
About the role
<div class="content-intro"><p class="ms-outlook-mobile-reference-message">Space is a warfighting domain. True Anomaly seeks those with the talent and ambition to build the technology that secures it.</p>
<p class="ms-outlook-mobile-reference-message"><u>OUR MISSION</u></p>
<p class="ms-outlook-mobile-reference-message">True Anomaly delivers decisive capabilities for space superiority. We build autonomous spacecraft, advanced payloads, mission software, and space-based interceptors — enabling the U.S. and its Allies to secure the space environment and counter threats from the ultimate high ground.</p>
<p class="ms-outlook-mobile-reference-message"><u>OUR VALUES</u></p>
<ul>
<li class="ms-outlook-mobile-reference-message"><strong>Be the offset.</strong><span class="Apple-converted-space"> </span>We create asymmetric advantages with creativity and ingenuity.</li>
<li class="ms-outlook-mobile-reference-message"><strong>What would it take?</strong> We challenge assumptions to deliver ambitious results.</li>
<li class="ms-outlook-mobile-reference-message"><strong>It’s the people.</strong> Our team is our competitive advantage and we are better together.</li>
</ul></div><p><u>YOUR MISSION</u></p>
<p><span class="TextRun SCXW195834967 BCX0" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW195834967 BCX0">True Anomaly is </span><span class="NormalTextRun SCXW195834967 BCX0">seeking</span><span class="NormalTextRun SCXW195834967 BCX0"> a talented and experienced Senior FPGA Developer to lead the architecture, implementation, and verification of complex FPGA-based systems for our spacecraft. In this role, you will own your technical domain end-to-end — from requirements capture and architecture definition through simulation, integration, and on-orbit support — while managing ambiguity and driving cross-team delivery with minimal oversight. You will define FPGA-to-CPU/SoC interface architectures, lead verification planning across full digital subsystems, and bring a system-aware perspective that balances performance, cost, and risk across disciplines. As a senior contributor, you will mentor peers, raise the technical bar across the team, and introduce </span><span class="NormalTextRun SCXW195834967 BCX0">new approaches</span><span class="NormalTextRun SCXW195834967 BCX0"> to complex problems. You will collaborate closely with avionics, embedded software, and test teams to build high-reliability, radiation-tolerant firmware solutions that are fielded on real spacecraft.</span></span><span class="EOP SCXW195834967 BCX0" data-ccp-props="{}"> </span></p>
<p><strong>RESPONSIBILITIES</strong></p>
<ul>
<li><span data-contrast="auto">Lead the architecture and implementation of complex FPGA systems with multiple clock domains, high-speed interfaces, and stringent reliability requirements</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Own end-to-end FPGA development: requirements capture, functional block definition, HDL coding, simulation, synthesis, timing closure, and hardware integration</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Lead multi-board digital backplane and payload data bus design, driving compliance, margin validation, and derating analysis</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Define and manage verification and validation plans for full digital subsystems, integrating FPGA verification activities with system-level test</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Define FPGA-to-CPU/SoC interface architectures and collaborate with embedded software teams on protocol design and integration</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Develop and integrate COTS and custom IP cores into complete, production-ready solutions</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Implement radiation mitigation strategies including TMR, ECC, and scrubbing for space applications</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Lead cross-team delivery of FPGA development milestones, managing dependencies and setting clear checkpoints</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Mentor peers and junior engineers, elevating design quality and development practices across the team</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Develop and maintain design documentation, ICDs, verification plans, and test reports</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Participate in all aspects of the product development lifecycle, from concept through production, integration, and launch</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><strong>QUALIFICATIONS</strong></p>
<ul>
<li><span data-contrast="auto">Bachelor's degree in Electrical Engineering, Computer Engineering, or related field</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">5+ years of professional experience in FPGA design and development</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Deep expertise in VHDL and/or Verilog and FPGA synthesis flows</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience with Microsemi/Microchip, Xilinx/AMD, or Intel/Altera FPGA families and associated toolsets</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience with simulation and verification tools such as ModelSim, QuestaSim, or similar</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience designing and implementing high-speed Ethernet interfaces in FPGA fabric, including MAC/PHY integration, UDP/TCP offload, and high-throughput data path design</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience with Layer 2 Ethernet switch development, including frame forwarding, VLAN handling, and port arbitration</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience with other high-speed serial interfaces (PCIe) and common bus protocols (SPI, I2C, UART)</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience with radiation mitigation techniques for space-grade digital logic</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Experience reading and interpreting electrical schematics and collaborating with hardware design teams</span><span data-ccp-props="{}"> </span></li>
<li><span data-contrast="auto">Excellent written and verbal communication skills</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><strong>PREFERRED SKILLS AND EXPERIENCE</strong></p>
<ul>
<li>Experience with spacecraft FPGA development and space-qualified or radiation-hardened device families (PolarFire, ProASIC3, SmartFusion2, etc.) </li>
<li>Experience defining and executing FPGA-to-CPU/SoC interface architectures in collaboration with embedded software teams </li>
<li>Familiarity with SpaceWire and other spacecraft-specific data bus standards </li>
<li>Familiarity with signal integrity analysis and high-speed digital design practices </li>
<li>Exposure to software development in C, C++, or Python for firmware integration and test scripting </li>
<li>Knowledge of schematic capture tools (Altium Designer preferred) </li>
<li>Experience working in a fast-paced, startup environment or a similarly dynamic setting </li>
</ul>
<p><strong>COMPENSATION</strong></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="none">Base Salary: </span></strong><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559739":160,"335559740":240}">$150,000-$220,000</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="none">Equity + Benefits</span></strong><span data-contrast="none"> including Health, Dental, Vision, HRA/HSA options, PTO and paid holidays, 401K, Parental Leave</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559739":160,"335559740":240}"> </span></li>
</ul>
<p><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559739":160,"335559740":240}"><em><span class="TextRun SCXW83253800 BCX0" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW83253800 BCX0">Your actual level and base salary will be </span><span class="NormalTextRun SCXW83253800 BCX0">determined</span><span class="NormalTextRun SCXW83253800 BCX0"> on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, location, and experience.</span></span></em><span class="EOP SCXW83253800 BCX0" data-ccp-props="{"335559739":0}"> </span></span></p>
<p><strong>ADDITIONAL REQUIREMENTS</strong></p>
<ul>
<li><strong><span class="TextRun SCXW237564176 BCX0" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW237564176 BCX0">Ability to </span><span class="NormalTextRun SCXW237564176 BCX0">maintain</span><span class="NormalTextRun SCXW237564176 BCX0"> or obtain </span><span class="NormalTextRun SCXW237564176 BCX0">TS//</span><span class="NormalTextRun SCXW237564176 BCX0">SCI clearance</span></span><span class="EOP SCXW237564176 BCX0" data-ccp-props="{}"> </span></strong></li>
<li><strong>Work Location</strong>— this role will be onsite at our Long Beach, CA location, with travel to other sites as needed.</li>
<li><strong>Work environment</strong>—the work environment; temperature, noise level, inside or outside, or other factors that will affect the person's working conditions while performing the job.</li>
<li><strong>Physical demands</strong>—the physical demands of the job, including bending, sitting, lifting and driving.</li>
</ul>
<p><span class="TextRun SCXW267002851 BCX0" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW267002851 BCX0">This position will be open until it is successfully filled. To </span><span class="NormalTextRun SCXW267002851 BCX0">submit</span><span class="NormalTextRun SCXW267002851 BCX0"> your application, please follow the directions below. #LI-Onsite</span></span><span class="TextRun MacChromeBold SCXW267002851 BCX0" lang="EN-US" data-contrast="none"> </span></p><div class="content-conclusion"><p>To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.</p>
<p>True Anomaly is committed to equal employment opportunity on any basis protected by applicable state and federal laws. If you have a disability or additional need that requires accommodation, please do not hesitate to let us.</p>
<p> </p></div>
Perks & benefits
- 401k
- Paid Time Off
- Equity Compensation
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