Principal Engineer, SI-PI

<p><span style="font-family: helvetica, arial, sans-serif;">We are <strong>CARIAD</strong>, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. To achieve that we are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million new vehicles per year. We’re looking for talented, digital minds like you to help us create code that moves the world. Together with you, we’ll build outstanding digital experiences and products for all Volkswagen Group brands that will transform mobility. Join us as we shape the future of the car and everyone around it.</span></p> <p><span style="font-family: helvetica, arial, sans-serif;">​<strong><u>Role Summary:</u></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​</u></strong>The Principal Engineer, SI/PI (Signal Integrity / Power Integrity) is the electrical performance expert for CARIADs high-speed automotive compute platforms (infotainment, ADAS ECUs). Scope spans compute modules and carrier boards, high-speed connectors/cables, and return-path/grounding considerations from concept through EVT/DVT/PVT. This role ensures clean high-speed signaling and robust power delivery across PCB, package, and system interconnects to prevent noise, jitter, data errors, EMI failures, and system instability. The engineer influences schematic and layout decisions early, builds predictive models and simulations, and validates designs in the lab—partnering closely with SoC vendors, hardware/layout, EMC, and system validation teams to meet performance, EMC, and reliability targets.</span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>Role Responsibilities:</u></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Own channel budgets and SI sign-off reports per interface/program (margin targets, assumptions, and waiver rationale).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Analyze and optimize high-speed channels (PCIe, DDRx, Ethernet, MIPI/SerDes) for loss, crosstalk, reflections, jitter, and margin.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Define routing/topology guidelines (impedance, spacing, length matching, reference planes) and review PCB layouts for compliance.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Partner with architecture and board teams to drive interface trade-offs and risk reductions early in design.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Signal Integrity Analysis &amp; Design Enablement</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Define PDN target-impedance specifications and PI sign-off reports per rail/domain (including transient/noise budgets).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Design and validate PDN across VRMs, planes, vias, and decoupling to meet target impedance and transient response goals.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Assess rail noise, droop/spike behavior, and coupling between power domains; recommend mitigation (placement, decaps, filters, sequencing).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Support power-up and load-step planning with system/SoC teams to ensure robust operation across use cases.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Maintain reusable SI/PI model library and simulation-to-measurement correlation reports; publish updated design rules/guard-bands.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Build and maintain SI/PI models (S-parameters, IBIS/IBIS-AMI, SPICE) and run what-if studies to predict risk before hardware build.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Use EM and circuit simulation tools (HFSS/SIwave/Sigrity/ADS or equivalents) to evaluate interconnects, packages, and planes.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Correlate simulation results to lab measurements and update models/rules to improve prediction accuracy.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Simulation, Modeling &amp; Correlation</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Produce lab measurement and correlation reports (eye/jitter/BER, PDN impedance/noise) and support pre-compliance EMI/EMC debug as needed.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Perform characterization using oscilloscopes, TDR, VNA, high-speed probing, and automated margining where applicable.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Debug electrical issues during bring-up and validation, including intermittent errors, eye closure, power noise-induced faults, and pre-compliance EMI/EMC issues.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Document root cause, corrective actions, and verification evidence to support release readiness.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Lab Validation, Bring-up &amp; Debug</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Own SI/PI sign-off checklist, waiver process, and 'golden' design-rule set; drive adoption across multiple boards/programs.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Lead design reviews and provide clear, actionable SI/PI sign-off criteria aligned with performance, EMC, and reliability targets.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Collaborate with EMC engineers to address emissions/susceptibility drivers tied to layout, grounding, shielding, and PDN behavior.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Mentor engineers and contribute to reusable design rules, checklists, and best-practice documentation across programs.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Cross-Functional Leadership &amp; Standards</span></li> </ul> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​General Skills:</u></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Technical leadership and systems-level thinking; able to influence design decisions across teams without direct authority.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Strong analytical and structured problem-solving skills; ability to diagnose complex electrical issues and drive closure.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Excellent communication skills (written, verbal, presentation) with ability to translate SI/PI findings into actionable design guidance.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Collaboration across global, cross-functional teams and suppliers; comfortable working across time zones.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">High attention to detail and quality mindset; able to balance technical trade-offs across performance, cost, schedule, and manufacturability.</span></li> </ul> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Required Specialized Skills:</u></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Deep experience with high-speed interfaces (e.g., PCIe, DDRx, Automotive Ethernet, MIPI/SerDes) and associated channel/receiver requirements.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Expertise in PCB stack-up, controlled-impedance routing, return-path design, via/connector modeling, and crosstalk/reflection mitigation.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Power delivery network (PDN) design and analysis including target impedance, decoupling strategy, VRM selection, and noise/droop control.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Hands-on simulation/modeling using SI/PI tools (e.g., Cadence Sigrity/SIwave, Keysight ADS, Ansys HFSS) and model types (S-parameters, IBIS-AMI, SPICE).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Lab proficiency with high-bandwidth oscilloscopes, TDR, VNA, probes/fixtures, and correlation of measurement to simulation.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Working knowledge of EMC/EMI principles as they relate to high-speed signaling, grounding, shielding, and power integrity in automotive ECUs.</span></li> </ul> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Desired Skills:</u></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Experience bringing high-speed compute boards/ECUs through EVT/DVT/PVT and into production, including design rule governance and supplier reviews.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Experience with advanced packaging or module integration (SoC package escape, connector/cable assemblies, harness considerations).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Familiarity with automotive development and compliance constraints (e.g., EMC test cycles, reliability validation, AEC-Q component considerations).</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Experience working with SoC vendors (e.g., Qualcomm, NVIDIA) on interface tuning, margining, and bring-up debug.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Background with scripting/automation for data analysis (Python, MATLAB) and reporting of SI/PI metrics.</span></li> </ul> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Workplace Flexibility:</u></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Hybrid work arrangement; on-site lab work required for bring-up, validation, and debug activities.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Occasional domestic and international travel (up to ~15%) to support supplier/SoC partner engagements, build events, and test labs as needed.</span></li> <li style="font-family: helvetica, arial, sans-serif;"><span style="font-family: helvetica, arial, sans-serif;">Meetings overlapping with European business hours as required for global coordination.</span></li> </ul> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Years of Relevant Experience:</u></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​</u></strong>12+ years of relevant experience in signal integrity/power integrity for high-speed digital systems (automotive, consumer electronics, or compute platforms).</span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Required Education:</u></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif;">​Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or related field (or equivalent practical experience).</span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>​Desired Education:&nbsp;</u></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif;">Master’s degree or PhD in Electrical Engineering or a related discipline.</span></p> <p><span style="font-family: helvetica, arial, sans-serif;"><strong><u>Compensation</u></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif;">Salary range is dependent on factors such as geographical differentials, credentials or certifications, industry-based experience, qualification and training. In the city of Mountain View, CA, the salary range for this position is $200,510.00 - $291,217.00.&nbsp;</span></p> <p><span style="font-family: helvetica, arial, sans-serif;">CARIAD, Inc. provides performance based merits and annual bonus along with a competitive benefits package. Benefits include medical, dental, vision, 401k with employer match and defined contribution plan, short and long term disability, basic life and AD&amp;D insurance, employee assistance program, tuition reimbursement and student loan repayment plans, maternity and non-primary caregiver leave, adoption assistance, employee referral program and vacation and paid holidays. We also offer a unique vehicle lease program that covers registration and insurance fees.&nbsp;</span></p> <p><span style="font-family: helvetica, arial, sans-serif;">CARIAD is an Equal Opportunity Employer.  We welcome and encourage applicants from all backgrounds, and do not discriminate based on race, sex, age, disability, sexual orientation, national&nbsp;origin, religion, color, gender identity/expression, marital status, veteran status, or any other characteristics protected by applicable laws.&nbsp;</span></p> <p><span style="font-family: helvetica, arial, sans-serif;">Employment with Cariad Inc. is contingent upon the successful completion of this screening process. We emphasize the importance of compliance with export control and sanctions laws as a fundamental aspect of our operations. Our company is dedicated to adhering to these regulations to ensure the lawful and ethical conduct of our business activities. Employment with our company is contingent on either verifying U.S. citizenship or U.S. lawful permanent resident status or obtaining any necessary license or confirming the availability of an applicable exemption or license exception. You, the applicant, will be required to answer certain questions for export control purposes, and that information will be reviewed by compliance personnel to ensure compliance with federal law. Cariad Inc. may choose not to apply for a license or use an applicable license exception (if available) for such individuals whose access to export-controlled technology or software source code may require authorization and may decline to proceed with an applicant on that basis alone.</span></p> <p><span style="font-family: helvetica, arial, sans-serif;">By submitting your application, you acknowledge and agree to participate in the export control and sanctions compliance screening process. Your cooperation in this matter is essential to our shared success and the integrity of our operations. Thank you for your understanding and commitment to upholding these important standards.</span></p> <p>&nbsp;</p>