Sr. Staff Engineer, Timing Methodology & Signoff

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Company Overview</strong></span></p> <p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p> <p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p> <p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p> <p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p> <p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p> <p>If that's you, join us — the intelligence everywhere revolution starts here.</p> <p>&nbsp;</p></div><div> <h3><strong>Build the silicon that powers the future of ultra-low-power computing</strong></h3> <p>At Ambiq, we’re redefining what’s possible at the edge—powering next-generation AI, wearables, and IoT devices with breakthrough ultra-low-power technology. We’re looking for a <strong>Sr. Staff Engineer – Timing Methodology</strong> to take a <strong>true ownership role</strong> in driving timing from architecture to silicon—and ensuring our designs don’t just work, but <em>excel</em> in real-world conditions.</p> <hr> <h2><strong>Why this role stands out</strong></h2> <p>This isn’t a “maintain the flow” role. You’ll:</p> <ul> <li>Own <strong>end-to-end timing convergence</strong> (block → SoC → post-silicon)</li> <li>Shape <strong>methodology, flows, and signoff strategy</strong></li> <li>Work on <strong>cutting-edge FinFET, multi-patterning nodes</strong>, and unique ultra-low-power challenges</li> <li>Directly influence <strong>PPA and product success</strong></li> </ul> <p>If you thrive on solving complex timing problems others shy away from—this is your playground.</p> <hr> <h2><strong>What You’ll Do</strong></h2> <ul> <li><strong>Own timing convergence end-to-end</strong>, from methodology definition to SoC signoff</li> <li>Develop and refine <strong>timing flows, constraints, and analysis methodologies</strong></li> <li>Drive <strong>block-level closure and SoC-level timing correlation</strong></li> <li>Lead <strong>signoff activities</strong>, including: <ul> <li>PVTR corner definition</li> <li>Timing margining &amp; ECO strategy</li> <li>Extraction and analysis</li> <li>Glitch/noise analysis &amp; power/timing tradeoffs</li> </ul> </li> <li>Partner cross-functionally with <strong>RTL, DFT, physical design, and IP teams</strong></li> <li>Define and manage <strong>timing constraints across diverse IP</strong> (std cell, memory, hard IP)</li> <li>Ensure strong <strong>pre-silicon to post-silicon correlation</strong> through close collaboration with bring-up and validation teams</li> <li>Continuously enhance <strong>automation, scripts, and methodologies</strong> to improve efficiency and scalability</li> <li>Stay at the forefront of <strong>STA advancements and emerging process technologies</strong></li> </ul> <hr> <h2><strong>What You Bring</strong></h2> <ul> <li><strong>8+ years</strong> of experience in timing analysis and convergence</li> <li>Deep expertise in <strong>static timing analysis (STA)</strong> using <strong>Synopsys Primetime or Cadence Tempus</strong></li> <li>Strong experience with <strong>block-level and SoC-level timing closure</strong> in advanced nodes</li> <li>Solid understanding of <strong>digital design fundamentals and timing principles</strong></li> <li>Hands-on experience with industry-standard <strong>EDA tools (Synopsys, Cadence)</strong></li> <li>Proficiency in <strong>TCL, Python, or similar scripting languages</strong></li> <li>Strong problem-solving skills and ability to drive complex issues to closure</li> <li>Excellent communication and collaboration skills across engineering teams</li> </ul> <p><strong>Nice to have:</strong></p> <ul> <li>Experience with <strong>PnR tools</strong> (Fusion Compiler, Innovus)</li> </ul> <hr> <h2><strong>What Success Looks Like</strong></h2> <ul> <li>Clean, predictable timing convergence across increasingly complex SoCs</li> <li>Strong correlation between <strong>signoff and silicon behavior</strong></li> <li>Scalable methodologies that improve team velocity and design quality</li> <li>Measurable impact on <strong>power, performance, and area (PPA)</strong></li> </ul> <hr> <h2><strong>Work Authorization</strong></h2> <p>Must be currently authorized to work in the United States. We are unable to sponsor or transfer visas for this role now or in the future.</p> <hr> <h2><strong>Why Ambiq</strong></h2> <p>We’re small enough that your impact is immediate—and big enough to be solving problems that rival the industry’s most complex SoCs. Our ultra-low-power innovation creates <strong>entirely new timing challenges</strong>, making this an opportunity to do some of the most interesting work of your career.</p> </div>