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FPGA Design Engineer II
HPR
Needham9h ago
- Seniority
- Mid
About the role
<p style="line-height: 1;"><span data-contrast="auto">HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we’re searching for a forward-thinking</span><strong><span data-contrast="auto"> FPGA Design Engineer </span></strong><span data-contrast="auto">to help us build the future of capital markets infrastructure.</span><span data-ccp-props="{}"> </span></p>
<p style="line-height: 1;"><span data-contrast="auto">As an</span><strong><span data-contrast="auto"> FPGA Design Engineer</span></strong><span data-contrast="auto"> at HPR, you will:</span><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Design, develop, optimize, and maintain high-performance FPGA compute and networking systems used in electronic trading</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Own the RTL design process from specification and coding through synthesis and FPGA implementation</li>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Partner with design verification engineers to review and execute comprehensive test plans</li>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration</li>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Contribute to improving our development processes, tools, and methodologies<span data-ccp-props="{}"> </span></li>
</ul>
<p style="line-height: 1;"><strong><span data-contrast="auto">Required Qualifications</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">3+ years of experience in digital logic design for FPGAs or ASICs</li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Proficiency in SystemVerilog (preferred) or VHDL</li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Deep understanding of computer architecture and digital design concepts</li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi)</li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Comfortable working in a Linux environment</li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Strong problem solving, debugging, and communication skills<span data-ccp-props="{"134233117":true,"134233118":true}"> </span></li>
</ul>
<p style="line-height: 1;"><strong><span data-contrast="auto">Desired Qualifications</span></strong><span data-ccp-props="{"134233117":true,"134233118":true}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Experience working with Xilinx and/or Altera FPGAs</span></li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Familiarity with FPGA architecture and advanced design techniques, including optimizations for synthesis and timing closure</li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">In-depth knowledge of networking protocols (IP, TCP, UDP)</li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience with high-speed interfaces (PCIe, Ethernet, and/or DDR)</li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Familiarity with C programming and scripting in Python and/or Perl<span data-ccp-props="{"134233117":true,"134233118":true}"> </span></li>
</ul>
<p><strong>Compensation: </strong>In compliance with Massachusetts law, the anticipated annual base salary range for this position is $129,000 to $166,000. Please note that this range represents the expected base salary for this role at the time of posting. The final offer may vary based on factors such as the candidate's experience, skills, and qualifications. This range does not include other forms of compensation such as potential bonuses, equity, or benefits.</p>
<p><em><span data-contrast="auto">This position requires being on-site at our office in Needham, MA full-time (5 days per week)</span></em><span data-ccp-props="{"134233117":true,"134233118":true}"> </span></p>
<p style="line-height: 1;"><em><span data-contrast="auto">HPR does not currently provide employment sponsorship</span></em><span data-ccp-props="{"134233117":true,"134233118":true}"> </span></p>
<p style="line-height: 1;"><span data-ccp-props="{}"> </span></p>
Perks & benefits
- Equity Compensation
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