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Senior FPGA Engineer
Freeform
Los AngelesOn-site1w ago
- Seniority
- Senior
About the role
<h2><span style="font-size: 14pt;">SENIOR FPGA ENGINEER</span></h2>
<p><span data-contrast="auto">Freeform builds AI-native manufacturing systems that unify software, hardware, and physics to produce industrial-scale parts at the speed of human ideation. By treating manufacturing as a single integrated system, we unlock a new era of innovation where complex hardware is designed, built, and scaled without limits.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></p>
<p><span data-contrast="auto">As a Senior FPGA Engineer at Freeform, you will be a key technical contributor on our next-generation compute platform, a distributed system of hundreds of FPGAs orchestrating many dozens of high-power lasers in real time. This is not a standard FPGA role. You will be working at the boundaries of what’s physically possible with reconfigurable compute: processing hundreds of thousands of frames per second through a real-time ML inference pipeline, with latency budgets that leave no margin for error. You will work with cutting-edge silicon including the Xilinx Zynq Ultrascale+ MPSoC, and tightly couple FPGA fabric with state-of-the-art GPUs as part of one of the most demanding heterogeneous computing platforms in existence.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></p>
<p><span data-contrast="auto">You will be a core builder of the FPGA platform at Freeform, designing new components, going deep on implementation, tackling hard problems across RTL, timing, and system integration, and having a major seat at the table on major architectural decisions. We are pioneering the use of FPGAs for real-time machine learning in an industrial manufacturing context, a space where almost no prior art exists. This is high-impact work at the frontier of what FPGA-based computing can do, and it sits at the heart of what makes Freeform’s technology unlike anything else in the world.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></p>
<p><span data-contrast="auto">3D printing experience is not required to be successful here - rather we look for smart, motivated, collaborative engineers who love solving hard problems and creating amazing technology!</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></p>
<p><iframe src="https://www.youtube.com/embed/sXfG6ssZ190" width="560" height="314"></iframe></p>
<p><strong>Responsibilities:</strong></p>
<ul>
<li><span data-contrast="auto">Design, implement, and optimize subsystems within a massively parallel, ultra-low latency FPGA pipeline processing hundreds of thousands of frames per second across a fleet of hundreds of FPGAs</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Collaborate closely with software, electrical, and process engineering teams to build and advance FPGA capabilities at the system level</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Build and optimize real-time ML inference pipelines directly on FPGA fabric, one of the most demanding and least-explored frontiers in reconfigurable computing</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Develop RTL components and IP blocks with rigorous attention to timing closure, resource utilization, and deterministic latency</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Implement high-performance signal processing algorithms on FPGA, including custom arithmetic, filtering, and feature extraction at line rate</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Implement deterministic, nanosecond-precision controllers for high-power laser systems operating under strict real-time constraints</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
</ul>
<p><strong>Basic Qualifications:</strong></p>
<ul>
<li><span data-contrast="auto">Bachelor’s degree in computer engineering, electrical engineering, computer science, or related field </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">8+ years of FPGA development experience in SystemVerilog or VHDL </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Familiarity with Xilinx Vivado/Vitis toolchain development environment </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience with high-speed IO, board bring up, and similar hardware-centric FPGA development domains</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
</ul>
<p><strong>Nice to Have:</strong></p>
<ul>
<li><span data-contrast="auto">Master’s degree in computer engineering, electrical engineering, computer science, or related field </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience with image processing or DSP</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience with Xilinx Zynq Ultrascale+ MPSoC </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience with embedded software development including embedded Linux and System on Chip (SoC)-based architectures </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience implementing math/advanced computations on FPGAs </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Experience with heterogeneous computing platforms and high-speed data acquisition systems </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Familiarity with C/C++ or other high-level programming languages </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Excellent verbal and written communication skills </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Creative thinker able to apply first-principles reasoning to solve complex problems </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
</ul>
<p><strong>Location:</strong></p>
<ul>
<li><span data-contrast="auto">Based in Hawthorne, our vertically integrated facility brings technology development, R&D, and production together under one roof. We operate at the center of LA’s deep tech ecosystem, surrounded by some of the most ambitious hardware innovation happening anywhere in the country.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">Our fast-paced, cross-functional environment is built on close collaboration, and as such, this role requires full-time onsite presence (five days a week), with very limited exceptions.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
</ul>
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<p><strong>What We Offer:</strong></p>
<ul>
<li>We have an inclusive and diverse culture that values collaboration, learning, and making deliberate data-driven decisions.</li>
<li>We offer a unique opportunity to be an early and integral member of a rapidly growing company that is scaling a world-changing technology.</li>
<li>Benefits
<ul>
<li>Significant stock option packages</li>
<li>100% employer-paid Medical, Dental, and Vision insurance (premium PPO and HMO options)</li>
<li>Life insurance</li>
<li>Traditional and Roth 401(k)</li>
<li>Relocation assistance provided</li>
<li>Paid vacation, sick leave, and company holidays</li>
<li>Generous Paid Parental Leave and extended transition back to work for the birthing parent</li>
<li>Free daily catered lunch and dinner, and fully stocked kitchenette</li>
<li>Casual dress, flexible work hours, and regular catered team building events</li>
</ul>
</li>
<li>Compensation
<ul>
<li><span data-contrast="auto">As a growing company, the salary range is intentionally wide as we determine the most appropriate package for each individual taking into consideration years of experience, educational background, and unique skills and abilities as demonstrated throughout the interview process. Our intent is to offer a salary that is commensurate for the company’s current stage of development and allows the employee to grow and develop within a role.</span><span data-contrast="auto"> </span><span data-contrast="auto"> </span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
<li><span data-contrast="auto">In addition to the significant stock option package, the estimated salary range for this role is $160,000 - $250,000/year. The upper end of the range is reserved for individuals who demonstrate exceptional experience, deep domain mastery, and a proven history of high performance and impact.</span><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></li>
</ul>
</li>
<li>Freeform is an Equal Opportunity Employer that values diversity; employment with Freeform is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.</li>
</ul>
Perks & benefits
- 401k
- Vision Insurance
- Paid Time Off
- Equity Compensation
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