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About the role
<p>We’re looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. This role blends architecture design, hands-on implementation, and technical leadership. You’ll collaborate across engineering teams to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.</p>
<p><strong>Responsibilities</strong></p>
<ul>
<li>Define HW architecture and evaluate design trade-offs for performance, area, and power.</li>
<li>Lead RTL development, integration, and verification throughout the design cycle.</li>
<li>Partner with firmware and verification teams to ensure top-quality silicon delivery.</li>
<li>Mentor and review junior engineers’ work, promoting best practices and technical excellence.</li>
<li>Provide design-in and bring-up support, including technical expertise for customer-facing projects.</li>
</ul>
<p><strong>Qualifications</strong></p>
<ul>
<li>Strong command of SystemVerilog for RTL design and digital architecture.</li>
<li>Experience using simulation tools such as Questa, Incisive, or VCS.</li>
<li>Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.</li>
<li>Proven experience in ASIC or FPGA design, synthesis, and timing closure.</li>
<li>Strong analytical thinking and communication skills, with the ability to manage complex priorities.</li>
<li>10+ years of relevant experience and a BSEE or MSEE degree.</li>
</ul>
<p><strong>Preferred / Plus</strong></p>
<ul>
<li>Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.</li>
<li>Familiarity with UVM-based verification environments.</li>
<li>Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).</li>
<li>Understanding of AMBA AXI or CHI protocols.</li>
</ul>
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