Back to all jobs
E
- Employment
- Full-time
- Seniority
- Staff
About the role
As a Sr Staff / Principal Physical Verification Engineer, you will be the technical owner of all signoff physical verification activities across advanced process nodes. You will lead DRC, LVS, and DFM sign-off at chip top level, drive hierarchical verification strategies, and own bump planning and package-level DRC across Intel, TSMC, Samsung, and GlobalFoundries technologies spanning 28nm through 2nm. You will be a partner with physical design, package engineering, and foundry teams to ensure first-pass tape out success on chiplet-based products.
756,000+ hidden jobs like this
eliyan and thousands of companies post here first — often days before LinkedIn or Indeed. Your first 5 applications are free; go Pro to apply without limits.
Everything Pro unlocks:
- Unlimited applications — free stops at 5
- Track every application in one place
- Apply straight to the source, one click
- Save & organize roles you love
- Roles pulled from company boards before the big sites
