Junior Physical Design Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary<strong> Junior Physical Design Engineer</strong> to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.</p> <p>As a <strong>Junior</strong> <strong>Physical Design Engineer</strong>, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li class="text-start "> <p><strong>Physical Implementation &amp; Execution</strong></p> <ul> <li class="text-start ">Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards</li> <li class="text-start ">Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place &amp; Route, and Clock-Tree Synthesis (CTS)</li> <li class="text-start ">Own macro-level implementation with deep hands-on experience in floorplanning and complex routing</li> </ul> </li> <li class="text-start "> <p><strong>Signoff &amp; Design Integrity</strong></p> <ul> <li class="text-start ">Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)</li> <li class="text-start ">Ensure first-pass silicon success through rigorous signoff flows and analysis</li> <li class="text-start ">Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness</li> </ul> </li> <li class="text-start "> <p><strong>Methodology Development &amp; Cross-Functional Collaboration</strong></p> <ul> <li class="text-start ">Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation</li> <li class="text-start ">Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity</li> <li class="text-start ">Leverage scripting and automation to make engineering environment faster and more robust</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <p></p> <div> <ul> <li>Bachelor’s degree in Electrical Engineering or a related technical field</li> <li>Foundational understanding of the RTL-to-GDS flow, with academic or internship exposure to areas such as floorplanning, placement, and routing</li> <li>Familiarity with advanced process technologies (e.g., 7nm and below) through coursework or hands-on projects</li> <li>Basic experience with signoff methodologies and tools, including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis</li> <li>Working knowledge of TCL or Python scripting for simple automation and support of EDA tool flows</li> </ul> </div> <p><strong>Preferred Qualifications</strong></p> <ul> <li class="text-start ">Experience with full-chip level implementation and integration</li> <li class="text-start ">Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon</li> <li class="text-start ">Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout</li> <li class="text-start ">Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)</li> <li class="text-start ">Background in high-speed interface designs or connectivity protocols</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>