Senior/ Staff Physical Design Engineer - EMIR CAD

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.</p> <p data-path-to-node="4">This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.</p> <p data-path-to-node="5">You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.</p> <p><strong><span data-contrast="none">Key Responsibilities</span></strong></p> <ul> <li data-path-to-node="7,0,0">Take responsibility on IR drop analysis and signal/power electromigration (EM) flow</li> <li data-path-to-node="7,1,0">Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)</li> <li data-path-to-node="7,3,0">Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks</li> <li data-path-to-node="7,4,0">Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow</li> <li data-path-to-node="7,5,0">Understand root-cause analysis for voltage drop violations and EM risks</li> <li data-path-to-node="7,7,0">Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data</li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li data-path-to-node="9,0,0">Bachelor's or Master's degree in Electrical Engineering or a related technical field</li> <li data-path-to-node="9,1,0">5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products</li> <li data-path-to-node="9,2,0">Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)</li> <li data-path-to-node="9,3,0">Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)</li> <li data-path-to-node="9,4,0">Basic understanding of Place &amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture</li> <li data-path-to-node="9,6,0">Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing</li> <li data-path-to-node="9,6,0">Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override)</li> <li data-path-to-node="9,6,0">Strong understanding of required inputs for creating Scenarios and Analysis Views</li> <li data-path-to-node="9,6,0">Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof)</li> </ul> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <ul> <li data-path-to-node="11,2,0">Experience performing Chip-Package-System (CPS) thermal and power co-simulation</li> <li data-path-to-node="11,3,0">Familiarity with thermal analysis tools and their interaction with electrical performance</li> <li data-path-to-node="11,4,0">Experience working with sign-off criteria and margins for high-volume production chips</li> <li data-path-to-node="11,4,0">Basic understanding of timing and P&amp;R</li> <li data-path-to-node="11,4,0">Good understanding of EM, including deterministic EM (DC, peak, RMS)</li> <li data-path-to-node="11,4,0">Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF)</li> <li data-path-to-node="11,4,0">Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution</li> </ul> <p></p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>