Post Silicon Validation Engineer

<p><strong>What You Will Do:</strong></p> <p><strong>Get ready to dive into an exhilarating journey as you work on the bring-up, validation, and debugging of a groundbreaking interference accelerator chip/chiplets! Here’s what you can look forward to:</strong></p> <ul> <li>Work on chip(s) bring up, validation and debug of cutting-edge interference accelerator chiplet. This includes cutting-edge technology: test and validate high-speed serial protocols like PCIe Gen5, high-speed memory interfaces such as LPDDR5, and die-to-die chiplet interconnect blocks.</li> <li>Innovate and execute:** Create and implement comprehensive test bring-up and validation plans alongside your dynamic team, develop automated randomization of software/firmware kernel functions and logging instrumentation in conjunction with self-checking post processors</li> <li>Craft impactful test scripts:** Develop test scripts and embedded firmware functions for host systems that will test and validate aspects of our high-speed interfaces, including PCIe, LPDDR, and D2D, pushing the boundaries of what's possible.</li> <li>Equip your workspace: Collaborate with your team to procure and acquire the latest lab equipment, ensuring you have the tools needed to succeed.</li> <li>Collaborate and conquer:** Work hand-in-hand with hardware, software, and operations teams on exciting challenges such as ATE tests and hardware/software debugging, fostering a spirit of teamwork and innovation.</li> </ul> <p><strong>What you will bring:</strong></p> <ul> <li>Do you have the following qualifications and Experience?</li> <li>BS/MS in Electrical/Computer Engineering with 5 + years industry experience working with high performance SoC</li> <li>Familiarity with high speed serial protocol (such as PCIe Gen3/4/5) and/or high speed external memory technology (such as LPDDR3/LPDDR4/LPDDR5 and/or high speed I/O standards.</li> <li>Excellent debugging verbal and written communication skills</li> <li>Capable of working effectively across cross functional organizational boundaries.</li> </ul>