Senior RTL Design Engineer

<p><strong>Responsibilities:&nbsp;</strong><br>&nbsp;• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.&nbsp;<br>&nbsp;• Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.&nbsp;<br>&nbsp;• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.&nbsp;<br>&nbsp;• Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.&nbsp;<br>&nbsp;• Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.&nbsp;</p> <p><strong>Requirements:&nbsp;</strong></p> <p>&nbsp;• 8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.&nbsp;<br>&nbsp;• Expertise in CPU processor designs in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; scalar and/or vector execution units; load-store unit; cache and memory subsystems.&nbsp;<br>&nbsp;• Knowledge of RISC-V architecture is a plus.&nbsp;<br>&nbsp;• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.&nbsp;<br>&nbsp;• Experience with Scala and/or Chisel is a plus.&nbsp;<br>&nbsp;• Attention to detail and a focus on high-quality design.&nbsp;<br>&nbsp;• Ability to work well with others and a belief that engineering is a team sport.&nbsp;<br>&nbsp;• Knowledge of at least one object-oriented and/or functional programming language.&nbsp;<br>&nbsp;• Background of successful CPU development from architecture through tapeout.</p> <p style="line-height: 1;">&nbsp;• MS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.</p> <p style="line-height: 1;">#LI-DNI</p>