Lead RTL Engineer (CPU & Processor Design)

Gramian Consultancy is a boutique consultancy specializing in IT professional services and engineering talent solutions. With a strong background in software engineering and leadership, we help companies build high-performing teams by matching them with professionals who truly fit their needs.

Role Overview

We are partnering with an innovative semiconductor company developing next-generation compute technologies. The team is building advanced processor architectures and is seeking an experienced RTL leader to drive implementation from architectural specification through tapeout.

We are looking for a hands-on Lead RTL Engineer with deep expertise in CPU and processor design, SystemVerilog, microarchitecture, and silicon development flows. This role combines technical leadership with individual contribution, requiring ownership of RTL implementation, synthesis, timing closure, and coordination across architecture, verification, and physical design teams. You will play a key role in driving the path from RTL development to successful GDSII handoff.

CONTRACT: long-term engagement Contractor or FTE (depending on the country)

COMMITMENT: Full-time

LOCATION: Remote or Hybrid — Preference for Austin, Texas (USA) and Bengaluru (India); exceptional candidates worldwide will be considered

PROCESS: Introductory Call → Three Client Interview Stages

NOTES: Candidates must have led RTL development for processor, CPU, DSP, or datapath-intensive silicon programs through tapeout.

Responsibilities:

• Translate the architecture specification into synthesizable SystemVerilog
• Own the RTL coding standards, linting rules, and design methodology
• Lead a team of 5-7 RTL engineers through the full design cycle
• Own the synthesis flow (Design Compiler or Genus) and drive timing closure
• Define and maintain SDC timing constraints
• Review all RTL code submissions for correctness, synthesizability, and style
• Coordinate with the outsource partner on GDSII handover (netlist, constraints, floorplan guidance)
• Work closely with the verification team to resolve bugs and achieve coverage closure

Requirements

• 7+ years of RTL design experience using SystemVerilog
• Proven experience leading RTL development for processor, CPU, DSP, or datapath-intensive designs
• Experience delivering at least one silicon tapeout through GDSII handoff
• Strong synthesis and timing closure experience using industry-standard EDA tools
• Deep understanding of microarchitecture and hardware design principles
• Experience with advanced semiconductor process technologies (28nm or below preferred)
• Ability to lead engineering teams while remaining highly hands-on technically
• Strong communication and technical leadership skills