Signal Integrity Engineer

<p><span style="font-size: 14pt; font-family: helvetica, arial, sans-serif;"><strong>About Graphcore</strong></span></p> <p><span style="font-size: 14pt; font-family: helvetica, arial, sans-serif;"><span data-contrast="none"><span data-ccp-charstyle="normaltextrun"><span data-teams="true">At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</span><br><br></span></span></span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><strong>Job Summary&nbsp;<br><br></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">As a hardware signal integrity engineer you will develop, extract and simulate PCB structures to ensure that the high speed SERDES (112Gbps) and DDR interfaces perform correctly within the system budget.&nbsp;</span></p> <p>&nbsp;</p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">You will work closely with the PCB and package substrate CAD engineers to design component signal launches from BGA components and connectors, layer transition via structures, and cable interconnect. You will define the low-loss materials to be used for future designs and work closely with Graphcore’s system architecture team and suppliers to ensure the best possible performance is achieved. You will be an expert user of high-speed PCB simulation tools and be familiar with industry best practice in high-speed digital system design.</span></p> <p>&nbsp;</p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><strong>The Team</strong></span></p> <p>&nbsp;</p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Graphcore’s Hardware Engineering Team creates both products for sale in volume production and hardware test &amp; validation systems based on Graphcore’s IPU processor.</span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">These systems allow Graphcore’s customers to develop leading-edge machine-leaning solutions for training and inference.</span></p> <p>&nbsp;</p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><strong>Responsibilities and Duties<br><br></strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Signal and Power Integrity specialist for the development of production systems and test boards for Graphcore’s family of processors.</span><br><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Includes:</span></p> <ul> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Development of printed circuit board structures for high frequency (112Gbps, 16Gbps) SERDES interfaces, DDR interfaces&nbsp;</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">PCB stackup definition</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">System, PCB and substrate level simulation and analysis of signal and power integrity</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Graphcore Integrated Circuit device interface requirements definition, tool &amp; vendor relationships</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">PCB design requirement and constraint definition, PCB layout supervision</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Prototype bring-up, evaluation, validation &amp; system test</span></li> </ul> <p>&nbsp;</p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><strong>Candidate Profile&nbsp;</strong><strong><br><br></strong></span></p> <ul> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">5+ years’ experience in high-speed digital circuit development, with a deep understanding of signal and power supply integrity</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Knowledge of high-speed circuit design requirements to ensure signal integrity and robust rejection of interference and crosstalk is essential</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Experience of high frequency (tens of GHz) SERDES design and validation</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Experience with ANSYS SIWave, HFSS, and/or Mentor Hyperlynx Signal and Power Integrity tools</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">High speed processor system design with experience in interfaces such as SERDES, PCI, DDR, Ethernet, etc.</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Design of BGA &amp; connector pad launches, via structures and transmission lines for GHz signals.</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">This position will require extensive practical work in the lab, bringing up, debugging and validating designs</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Expertise in the use of vector network analysers, high speed digital oscilloscopes, signal generators</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">A rigorous approach is required to make sure designs will work correctly the first time</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Independent working and the taking of responsibility, with excellent cooperative and communications skills to work in a small team environment</span></li> <li style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">Experience working in a small team, which requires a wide range of skills, an eagerness to participate in all parts of the development cycle from concept to testing in the lab and supporting manufacture and customers.&nbsp;</span></li> </ul> <p><span style="font-size: 14pt; font-family: helvetica, arial, sans-serif;"><span data-contrast="none"><span data-ccp-charstyle="normaltextrun"><br><br><br></span></span></span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;"><strong>Benefits</strong></span></p> <p><span style="font-family: helvetica, arial, sans-serif; font-size: 14pt;">In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.</span></p> <p>&nbsp;</p> <p>&nbsp;</p>